1. Field of the Invention
This invention relates to circuit arrangements in CHL technique, and more particularly to such arrangements in which individual CHL arrangements are arranged in an epitaxial layer and each includes an emitter, an output collector and control collectors.
2. Description of the Prior Art
Circuit arrangement in CHL technique are known in the art. They are described, for example, in the publication IEEE International Solid State Circuits Conf. 1974, pp. 18, 19 and 216. These arrangements, however, have a relatively large surface requirement.
Current hogging logic (CHL) functions are implemented by multi-collector pnp (or npn) transistor structures in integrated standard bipolar technology. The basic CHL element has an additional collector zone between the emitter zone and the output collector zone, the additional collector zone constituting a control collector. Under floating conditions, the control collector zone acts as an emitter zone, injecting carriers being collected at the output collector zone. Under the influence of a biasing voltage with respect to the emitter zone, the control collector zone hogs the carriers which were collected by the output collector zone, so that there is only the junction leakage current at the output collector zone. The resulting currents are defined to be the logic variables. Usually, the polarity of the output current is inverted by an output transistor and, according to the present invention, such an output transistor is omitted.